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Group: IT Recruiters | Technical Recruiters | Staffing Subject: Richardson Gollapalli posted a job: "Job: Component Design Engineer, in Phoenix, AZ Component Design Engineer, IRVINE ca Rate ai Duration: 7-18 months   USC or GCs are highly encouraged to apply as per the needs of client.   Mid to senior level resource needed Solid knowledge of ASIC design flows and methodologies Solid knowledge of ASIC verification methodology Experience writing micro-architecture spec Experience converting micro-architecture spec to RTL design Solid knowledge of RTL coding for synthesis using Verilog Solid knowledge of RTL coding for DFX Experience with Synopsys Design Compiler Experience with Timing analysis and timing closure Experience with gate level simulations and debug Excellent written and verbal communication skills Required Tool knowledge: VCS, Design Compiler (synthesis) Verilog/System Verilog, Unix C-shell, Source Code Management Architecture: IA, ARM, embedded controllers Protocols: DDR, PCIE, AMBA Tools: Lint, FPV, Perl, Tcl   Project Description: This is a memory expansion chip design for use in our high end server platforms. Daily Responsibilities: RTL coding to implement chipset functionality per Cspec, HAS, MAS. Work closely with pre-si validation team to debug failing tests; work closely with Physical Design team to resolve timing closure issues. Document functionality, usage models as required to support stakeholders.     Thank Regards, Richard | Sr.IT Recruiter  | www.sulaan.com richard@sulaan.com|480-626-0604 (work) | 480.452.1970 (fax) | Sulaan Solutions, Inc. Consulting | Staffing | Outsourcing http://bull.hn/l/116LN/2"

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