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k Rajeshwar posted a job: ASIC Verification and Validation with Verilog // Folsom, CA // Long Term Contract. "Hi Friends, Hope you are doing great. This is Rajesh from NYTP. I wanted to let you know about New Job opening in Folsom, CA. It is a Long Term Contract. Role : ASIC Verification and Validation with Verilog Location : Folsom, CA Duration : Long Term Contract. Job Description: Must have: • Hands on knowledge of System Verilog • Hands on working knowledge of methodologies like VMM, OVM, eRM • Strong hands-on experience on SOC projects. • Good experience in Full chip SOC and unit level validation. • Good knowledge of digital design concepts • Good knowledge of ASIC design flow • Hands on knowledge of complete ASIC Front-end verification flow – Verification planning to closure. • Good knowledge of Verilog/VHDL • Experience in defining verification plan • Experience in building re-usable verification environment • Understand the concept of random test generation and coverage • Experience on coverage points and SV assertion • Good team player and ability to work with stakeholders like RTL team, DFT team and Physical Design team • Good hands on knowledge of Gate level simulations (with back annotated delay values) • Good hands on knowledge of Planning and execution of IP level and fullchip verification Nice to have: • Experience on Intel SOCs • Experience on X86 Experience Required ( In Years) A minimum 2 years of experience in developing, implementing or architecting information systems with listed responsibilities and skill sets. If you are available and interested in this positions. Please send me an updated resume. Please feel free to contact me for any further information. Thanks and Regards, Rajesh Kaluri New York Technology Partners - Rochester 332 Jefferson Rd Rochester, NY 14623 T: 404 380 1796 F: 201-474-8533 raj@nytpartners.com www.nytp.com" | |||||
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Friday, September 6, 2013
New job ASIC Verification and Validation with Verilog // Folsom, CA // Long Term Contract.
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